High-speed interface links connecting two devices over a physical cable are typically serial communication links. Examples for such links include, but are not limited to, a high-definition multimedia interface (HDMI), a digital video interface (DVI), DisplayPort (DP), Universal Serial Bus 3 (USB3), and others.
During the process of data transmission, a transmitter continuously transmits signals to a receiver over the physical medium (cable). Typically, the physical cable exhibits the characteristics of a low-pass filter. Therefore, the amplitude of the data, received at the receiver, is attenuated and the phase is distorted. Also, the physical cable typically consists of wires which are not perfectly shielded. Thus, noise is present in the data due to cross coupling between signals from different wires.
The process of correcting the cable induced distortion is called equalization. This process can be performed by a decision feedback equalizer (DFE) that suppresses distortions caused by previously transmitted signals according to the continuously estimated impulse response of the interface between the transmitter and receiver. In practice, a DFE equalizes signals based on various parameters, such as digital filter taps or feedback coefficients, which are adjusted on the basis of estimated channel characteristics. The feedback coefficients are set to subtract the effects of interference from signals (e.g., symbols) that are adjacent in time to the desired signal (symbol). Typically, the coefficients are selected and adjusted using a least mean squares (LMS) algorithm.
An exemplary diagram of a decision feedback equalizer (DFE) 100 is provided in FIG. 1. The feedback filter 110 is used to adjust the tap coefficients. The number of feedback coefficients in the feedback filter 110 determines the number of previous symbol decisions which affect the current DFE decisions. With this aim, the feedback filter 110 attempts to model the distortion in a current signal to be equalized (input signal In) based on previously transmitted symbols using an LMS algorithm. A slicer 120 detects the value of the symbol that best corresponds to a value Outn that an adder 130 outputs to detect a symbol signal SYM. A difference between the input to the slicer 120 Outn and the output of the slicer 120 SYM is the symbol error En computed by an adder 140. In an ideal system, the symbol error En should essentially be zero. That is, the output Outn of the adder 130 should correspond to the received signal (In) for the current symbol. The voltage levels generator 150 presets the reference voltage levels that define the crossing points of the slicer 120.
Transmitted serial signals can be modulated using, for example, N-pulse amplitude modulation (PAM-N), where N discrete voltage levels are used to encode input bits. The two common PAM techniques utilized to modulate high-speed serial signals are PAM-2 (also known as non-return-to-zero “NRZ”) or PAM-4. In a PAM-2, two levels are used to encode a single bit. In a PAM-4, two bits are mapped to one of four possible differential voltage levels, for example, +3 volts, +1 volt, −1 volt, and −3 volts. Demodulation is performed by detecting the amplitude level of the carrier at every symbol period. The PAM-4 allows transmitting signals at double the rate of the PAM-2 signal, but the loss of PAM-4 modulated signals is higher than that of PAM-2 modulated signals. Experiments have shown that when the loss of the physical medium is more than 10 dB, the PAM-4 had been used in preference to PAM-2.
When a receiver includes a DFE, such as DFE 100, the mapping of an input PAM-4 signal to two output bits is performed by means of the slicer 120. With this aim, the slicer 120 includes three comparators (not shown). An equalized signal is compared to three different reference voltage levels VREF1, VREF2, and VREF3. Each comparator compares an equalized PAM-4 signal to one of the reference voltage levels VREF1, VREF2, and VREF3. Each reference voltage level (VREF1, VREF2, or VREF3) is typically set relative to a common-mode voltage level. Then, the 2 bits modulated in the PAM-4 signal are determined based on the crossing of the reference voltage levels VREF1, VREF2, and VREF3.
The voltage levels generator 150 sets the reference voltage levels VREF1, VREF2, and VREF3. These levels are set to nominal values to achieve proper detection of the signal. However, the comparators include an embedded offset that may bias the decision. Such an offset is a function of many parameters including, for example, manufacturing/fabrication attributes. To compensate for the comparator offset, the DFE should implement an offset cancellation mechanism which requires additional complex circuitry to the DFE.
The input signal is transmitted through a cable that determines, in part, the attenuation of the signal. Therefore, a gain is applied to the input signal to bring the level of the input signal to nominal decision levels. This is performed during power-up of the receiver by means of a variable gain amplifier (VGA) 160. Setting the gain by the VGA 160 also determines the sensitivity of the receiver. The VGA 160 is set during a power-up of the receiver. However, the attenuation of the cable may be changed during normal operation of the receiver, for example, due to a temperature change at the cable environment, wear and tear of the cable, and so on.
Therefore, it would be advantageous to provide an efficient solution for adaptively setting the gain and decision level of a PAM-N DFE.